Q. (a) VHDL code for DFF with active high enable, asynchronous active low reset, and synchronous active high set (D, E, Clk, Q, S, R are all std_logic):

--D Flip flop with active high enable

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFF is
Port ( D : in STD_LOGIC; --Data input
      E : in STD_LOGIC; --Enable
      Clk : in STD_LOGIC; --clock signal
      S : in STD_LOGIC; --Set flip flop
      R : in STD_LOGIC; --Reset flip flop
      Q : out STD_LOGIC); -- Flip flop output
end DFF;

architecture Behavioral of DFF is

--internal signal for storing flip flop Data
signal Q_reg : STD_LOGIC;

begin

--process is sensitive to both Clock and Reset
--as reset is asynchronous

process(Clk,R)
begin

--Reset flip flop if R is active low
--Asynchronous Reset operation
if R = '0' then --If Reset
   Q_reg <= '0';

--Synchronous operation's
elsif rising_edge(Clk) then

      --Synchronous Set operation
      if S = '1' then --If Set
         Q_reg <= '1';
      --Synchronous Data loading operation
      elsif E = '1' then --If Enabled
         Q_reg <= D;
      -- Memory operation
      else
         Q_reg <= Q_reg;
      end if;

end if;
end process;

--Flip flop Output
Q <= Q_reg;

end Behavioral;

--code ends

I. Introduction For this assignment, you will test and debug an im...